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verilog-A model for counter (Read 8124 times)
smarty
Community Member
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Posts: 46
verilog-A model for counter
Aug 28
th
, 2008, 7:36am
Hi all,
I am designing a temperature sensor and I would need to design a counter. But I wanted to test my design using behavioral model (verilog-A) model of counter.
I am not an expert in modelling. Can anybody help me out on this.
I need a counter which takes in serial input and converts it into a 8-bit parallel data.
Thanks and Regards,
SBR
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jbdavid
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Posts: 378
Silicon Valley
Re: verilog-A model for counter
Reply #1 -
Aug 28
th
, 2008, 11:36am
if you are using Cadence tools there are two libraries of interest shipped with the tools, ahdlLib, and bmslib.. there are examples of what you are looking for in there.
Also there are examples here on this site that may help you out.
jbd
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jbdavid
Mixed Signal Design Verification
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smarty
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Posts: 46
Re: verilog-A model for counter
Reply #2 -
Aug 28
th
, 2008, 8:19pm
Hi jbd,
Thanks.. I am working with cadence. i will look for the two libraries u mentioned and also search this site, if I get a little bit more info.
Best Regards,
SBR
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