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IF Statements & source-drain symmetry (Read 1701 times)
littlenasboy
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IF Statements & source-drain symmetry
Sep 05th, 2008, 9:48am
 
I've implemented a source referenced MOSFET model in Verilog-A, and I'm worried about source-drain symmetry.  

Can I just use IF statements in my model to address this problem, or will that lead to other issues?
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Geoffrey_Coram
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Re: IF Statements & source-drain symmetry
Reply #1 - Sep 8th, 2008, 5:31am
 
You can just use if statements, but you should verify for yourself that the equations you've written (and their derivatives) are continuous across the if statement.

If your simulator supports an ac analysis with a swept bias (instead of a swept frequency), you can easily check the ac currents from all four terminals as you sweep across vds=0.  Create 4 instances in your netlist, with an ac voltage source on a different terminal for each.
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