Peruzzi
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OK then. Looks to me like you need basic experience getting to know adders and schematics.
Surely you're not the only one in your community using Cadence and Verilog-AMS, right? You should also get some basic help from the person who maintains the design tools for your group. Here are the steps I would take. If you don't know how to do these steps, ask your tool admin. person to help you.
1. Go to a text book and quickly learn about adders. 2. Make a paper diagram of an 8-bit adder, so you have a gate level representation that you understand using AND, OR, XOR, INV, etc. 3. Snoop around with your Library Manager until you find the library with the digital gates, then create this adder circuit using your Cadence schematic tool. Make a symbol for the adder from your schematic. 4. Instantiate the symbol onto a testbench schematic page. Instantiate some pulse sources to make a sequence of test signals. 5. Use the Hierarchy Editor to create a config view of the testbench. If you use a Verilog-AMS simulator you can choose either the Verilog views or the schematic views of the logic gates you used to build the adder and test bench. 6. Get some local help to start and run the Verilog-AMS tool from the hierarchy editor.
I hope this is clear enough. Be sure to get some help from your colleagues using your specific design environment too.
Best of luck!
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