Hi mtech,

If you do a google search on full adder verilog you will find lots of examples.  A key point is that simulators which run Verilog-AMS can run Verilog (digital) as well.

Reply if you meant Verilog-A and not Verilog-AMS because the answer in that case is different.

Hi Mtech,

What do you plan to do with the model?  Some possibilities:

A:  Instantiate it in a digital system and simulate that with a digital simulator.
B:  Instantiate it in a mixed analog and digital system and simulate that with an AMS simulator.
C:  Instantiate the model by itself in a testbench and use it as a "golden reference" for designing the adder from top to bottom.

Tell me your plans for the model after you debug it and I'll help you from there.  The idea is to keep things as simple as you can get away with, right?

Best regards,

Bob

Is this a school assignment or are you working in industry.  If it is a school assignment, why don't you summarize that assignment for me.    What exactly is it you need to do?

OK then.  Looks to me like you need basic experience getting to know adders and schematics.

Surely you're not the only one in your community using Cadence and Verilog-AMS, right?  You should also get some basic help from the person who maintains the design tools for your group.  Here are the steps I would take.  If you don't know how to do these steps, ask your tool admin. person to help you.

1. Go to a text book and quickly learn about adders.  
2. Make a paper diagram of an 8-bit adder, so you have a gate level representation that you understand using AND, OR, XOR, INV, etc.
3. Snoop around with your Library Manager until you find the library with the digital gates, then create this adder circuit using your Cadence schematic tool.  Make a symbol for the adder from your schematic.
4. Instantiate the symbol onto a testbench schematic page.  Instantiate some pulse sources to make a sequence of test signals.
5. Use the Hierarchy Editor to create a config view of the testbench.  If you use a Verilog-AMS simulator you can choose either the Verilog views or the schematic views of the logic gates you used to build the adder and test bench.
6. Get some local help to start and run the Verilog-AMS tool from the hierarchy editor.

I hope this is clear enough.  Be sure to get some help from your colleagues using your specific design environment too.

Best of luck!

Mtech,

* See the person who maintains your Cadence tool installation for any details you don't understand.

* Yesterday you created a symbol and schematics for the 8-bit adder and simulated it successfully.  To simulate code instead of schematics, use the Library manager to create a Verilog view of the adder -- that same one you created the symbol and schematic for yesterday.  You don't need Verilog-AMS for a digital adder.  A text editor (vi by default) will open up.

* Google "8-bit adder Verilog", and find some examples of Verilog code for an 8-bit adder.  Study the code until you understand and feel comfortable with it.  Make your own version of that code, in the editor, with your own comments for your further reference.

* Save and quit, this will check and compile the code you pasted.  Make corrections as necessary.

* Use the same test bench you did yesterday.  Use the hierarchy editor to choose your newly created Verilog view instead of the schematics, and I think you're done!

Bob P.