sweet_julia
New Member
Offline
Posts: 6
|
Hi Frank,
I have read many threads from you about how to simulate the random jitter from device using PSS+Pnoise. Unfortunately, I didn't got consistent results from tdnoise and pnoise jitter.
I would like to describe my question here. The circuit I am simulating now consists of one input 16GHz buffer, divider, 4GHz buffer, CML MUX, 4GHz buffer, and one CML phase interpolator.
I set the noise type to "jitter". In the tdnoise, I could get the integrated output noise N. From the PSS, I could get the dv/dt at both rising edge and the falling edge. By using the equation in chapter 9, I could get the Jee ~200fs.
However, if I use the pnoise jitter directly, the integrated jee I got is around 400fs.
Do you have idea what causes this discrepancy?
You help is highly appreciated.
Regards, Julia
|