kidhyun
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Hi,
I have a question on the behavior of veriloga block in DC analysis. (DC sweep)
I have a veriloga block which looks like the following.
module X(in,out); ..... real var1;
analog begin @(initial_step) var1 = 0;
....
My question is if I do DC analysis sweeping 'in' voltage from, let's say, 0 to 1V with the step size of 0.1V, is 'initial_step' block called every time when the simulator runs DC analysis (11 times)? or Is that 'initial_step' called only when 'in' voltage is 0V (only at the start point of DC sweep)? (I only ran veriloga block with transient analysis, so I am a little bit confused.)
Thank You
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