ORNITORINCO
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Hello David,
thank you so much for your answer: I am still not a "cadence" guy, so I apologize for asking trivial questions! I am really trying to make my environment better, and I re-wrote the cds.lib file in order to include the syntax you suggested me, and it worked fine getting rid of the error. The only problem I had to face was to deal with the design kit cds.lib files to which I don't have write permission, and where the environment variable $CDS_INST_DIR iis used extensively. So I had to directly re-write them in the proper form inside my cds.lib and avoid INCLUDE statements to the original files.
At this point, though, it is not possible to simulate the Verilog-AMS file in the schematic of cadence ADE. Also, selecting ams from the simulators, I get an error saying that I need a config view for the file. I guess I need to understand better the verilog-AMS simulation flow. So, even though I don't want to ask for something it is written already in the (quite encyclopedic...) AMS Designer documentation, could anyone (please...) post a few lines in which it is clearly stated what are the tools I am supposed to setup in order to be able to simulate transistor level and Verilog-AMS blocks together? Is there any particular issues with design-kit (I use st90nmCMOS) that I should be aware of?
Thank you so much for any help!
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