Hello everyone,

after more than one year simulating my PLLs in Cadence icfb (mostly transistor level schematic blocks) and spending days and days waiting for transient simulations to be completed (mmw pll), I have decided to put all the necessary effort in moving towards Verilog-AMS.

Since I need to mix transistor level blocks with Verilog-AMS blocks, I thought the most intuitive way to do so is to generate symbols for Verilog-AMS blocks and use them together with the other transistor level blocks in the schematic and use Spectre to simulate the whole thing. The problem is that when I create a verilogams cellview using the icfb library manager, in the moment I close the editor I get several error from ncvlog:
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>DEFINE analogLib $CDS_INST_DIR/tools/dfII/etc/cdslib/artist/
>
>ncvlog: *W,DLCPTH (./cds.lib,13): cds.lib Invalid path '/tools/linsoft/lincad/ius58/tools/dfII/etc/cdslib/artist/analogLib' (cds.lib command ignored).
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the problem is that the environment variable $CDS_INST_DIR (already defined in the icfb configuration file .cshrc) is not '/tools/linsoft/lincad/ius58', since that is the IUS58 installation directory, and ncvlog substitutes $CDS_INST_DIR  with the wrong value.

Can anybody help on this?

Reading "The Designer's Guide to Verilog AMS" by K.Kundert and O. Zinke, I realized that I may need to use the AMS Designer tool. Is AMS Designer much better than icfb for analog/mixed-signal simulation?  

Thanks in advance for any help!

Francesco

Hello David,

thank you so much for your answer: I am still not a "cadence" guy, so I apologize for asking trivial questions! I am really trying to make my environment better, and I re-wrote the cds.lib file in order to include the syntax you suggested me, and it worked fine getting rid of the error. The only problem I had to face was to deal with the design kit cds.lib files to which I don't have write permission, and where the environment variable $CDS_INST_DIR iis used extensively. So I had to directly re-write them in the proper form inside my cds.lib and avoid INCLUDE statements to the original files.

At this point, though, it is not possible to simulate the Verilog-AMS file in the schematic of cadence ADE. Also, selecting ams from the simulators, I get an error saying that I need a config view for the file. I guess I need to understand better the verilog-AMS simulation flow. So, even though I don't want to ask for something it is written already in the (quite encyclopedic...) AMS Designer documentation, could anyone (please...) post a few lines in which it is clearly stated what are the tools I am supposed to setup in order to be able to simulate transistor level and Verilog-AMS blocks together? Is there any particular issues with design-kit (I use st90nmCMOS) that I should be aware of?

Thank you so much for any help!

thank you very much for your hint: I've got the AMS tutorial to work. And some work on the hdl.var file solved some issues I had with the DK models.

Thanks!