Rajdeep,

Let me give my opinion and guess on issues 1 and 3.

1. Spectre does not care whether I declare a port as voltage or electrical, It
always considers all the nodes as electrical in nature and thus expects conservative
models. For example, in modeling we might use s node voltage a signal
only to flag some events, so I am only worried about its voltage and not current!
But Spectre do care abt the current also!

Looks reasonable to me.  Spectre is an electrical simulator.  I'm guessing that a different algorithm solves the Verilog-A model and the ports must be electrical to interface with the Spectre circuit simulator.  

3. It also does not care whether one declares a port to be input or inout. Every port
is inout for it!!

This looks reasonable to me too.  It's a device-level circuit simulation after all.  Device elements which comprise circuits do not have inputs or outputs.  From the Spectre point of view the model must look like a device.  From the model's point of view, defining ports as input or output simplify the solution algorithm.

Best regards,

Bob P.

Hi Rajdeep,

I'm sure you're aware of this, but just a as a level-set, here're some terminologies:

It is the discipline of a conservative system that the user declares. One such discipline is electrical. Other disciplines could be mechanical, rotational etc. Each discipline has its potential and flow access functions (for the conservative system) that are defined by the natures associated with that discipline. For electrical discipline, voltage is the potential access function.

You are right that Spectre was designed to be one that simulated a conservative system. The other possibility that you alluded to would be one that simulated a signal-flow system in which only the potential nature is relevant.

Spectre does support $discontinuity() in Verilog-A, if that is what you are referring to. Is there a specific case of announcing discontinuity that is not working for you?

Regarding port direction, unless you're hooking your Verilog-A model to a digital design, the port direction in Verilog-A does not matter and is always inout. I tend to think of port direction specification as a documentation aid.

Regarding your comment in the last post about alternative to Spectre, have you considered writing real numbered models using, for example, VHDL real numbers or Verilog-AMS wreal that use the event-driven engine, and, assumes a signal-flow system.

Thanks,
Prabal.

Hi  Prabal,

Thanks for the  comments!
Yes, I know abt the discipline thing, and yes I would have loved to see spectre allowing us to write
a signa-flow model! Anyway, probably Verilog-A's main intention is to let designers write more
realistic conservative mdoels than signal-flow type of model, although keeping some of the features
for it.

But, discipline was treated as an undelcalred keyword. May be it's an older version!! Can you
please tell me the Spctre version you  have found discipline being accepted.

I do the same with the port direction! It kind of helps to understand ones intenstion of keeping a port in the model!

thanks,
Rajdeep

rajdeep wrote on Nov 24^th, 2008, 4:51am:


The header file "discipline.h" (or "disciplines.vams") has been part of the standard for years; please show us the code that you think isn't working.  I think you're perhaps misusing "discipline"

Hi Rajdeep,

$discontinuity(arg) should work just fine. If you are getting a syntax error, it's best if you post the original code, the version of software and the syntax error that you got.

Thanks,
Prabal.

I emphasized these points when I taught Verilog-A.

as an electrical conservative signal, all signals are bidirectional.. - Potential IN and FLOW out or vice-versa..
so the direction declaration in verilog a is only a convenience to match the port direction on the symbol (or which side of the symbol the pin defaults to)
the Electrical Network DOESN'T change when you change the port direction, so the simulation result is independent of it..

In reality there are no "input" or "output" wires.. there are just wires.
So thats how spectre behaves.

I think for what you want AMS is the proper solution, and except for simple mixed signal simulations SpectreVerilog just doesn't have language flexibilty to handle the hard cases quickly, so I JUST DONT USE IT!!

the simulators I use day in and day out are
spectre - AMSdesigner and NCsim..  All from ADE, just pick the right simulator (and everyone uses config views to control the netlisting today right? )

jbd