Hello everybody,

I have a general quesiton regarding the Monte Carlo analysis with Cadence application + TSMC 65n technology model file. When you run MC analysis with "process&Mismatch", will the simulator randomly pick up any cornor, then run mismatch at that particular cornor or will it run
some process and some mismatch (for example, 40 run for process and 60 runs for mismatch if you have a total 100 runs) analysis and then combine the data?

Thanks

N.X.

Each parameter which is varied will have two distributions, one for process, and one for mismatch. For each parameter, it will compute a random value using the process distribution for each point in the monte carlo. This is then effectively the mean about which the mismatch variation is then computed for each device in the circuit (for that monte carlo point).

So process and mismatch are computed for all points in the monte carlo.

Normally (at least this should be the goal), the statistical variation of the parameters should reflect a more realistic coverage of the process+mismatch distribution, and may never actually include the corners. I would say that corners-based design tends to lead to overly pessimistic (or overly cautious) design, because the corners are statistically very unlikely to occur - whereas if you look at the yield over all your monte carlo runs, you're going to get a more realistic picture. Note it doesn't mean that you need to get all points in the monte carlo simulation to meet the spec, but that you get a sufficient yield. If you use corners, you don't have much choice other than making sure all the corners meet the spec, because you don't know how close they are to failing, and so on.

In addition it's possible to have regions of failure which aren't covered by corner models.

That said, all of this is dependent on how good the statistical and corner models actually are!

Regards,

Andrew.

@Tlaloc, how do you intend to specify the corners? Is it by assigning sigma values to parameters or by specifying the exact location in the global variation?

I am running MC on 6t SRAM bit cell using Hspice and am stuck at the local variation. I am not able to specify the exact point at which it must do mismatch. For example, the worst case static noise margin was found to be 160mV from the Hspice output listing. Is there a way to tell Hspice to do mismatch variations around this point?