Seario
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Posts: 7
Michoacán
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Hello I'm new in this Verilog-A design world. And I'm here asking for your help. The program chose a capacitance value which depends of the initial voltage, at the beginning of this I had plenty of problems with the ddt function, reading some manuals such as varactor of this page I fix this problem (or at least I want to think that) . The problem is that I am not sure of the simulation result, can you please give some advice...
The codes for Verilog-A and spice are below...
`include "discipline.h"
module capvar(p,n); inout p,n; electrical p,n;
branch (p,n) cap;
// Parameters used in hysteresis part parameter real p1=1.272e-7; parameter real p2=-1.168e-6; parameter real p3=7.633e-5; parameter real p4=1.202e-5; parameter real p5=0.000176; parameter integer vt=15;
real Vd, cvar, cvar2, c, deriv;
analog begin Vd = V(p,n); cvar =(1/3)*p1*pow(Vd,3) +(1/2)* p2*pow(Vd,2) + p3*Vd; cvar2=(1/2)*p4*pow(Vd,2) + p5*Vd; if (Vd < vt) begin c = cvar; end else begin c = cvar2; end
deriv = ddt(c*Vd);
I(cap) <+ deriv;
end endmodule
I'm using smartspice to run Verilog-A
.verilog "prueba01.va"
* Initial source voltage Vg p 0 pulse (0V 25V 0 10n 10n 10n 100n)
* Function inside YVLGVAR p n capvar
* Load resistor between the node and GND R1 n 0 1M
* Sweep analysis .tran 5n 900n
*Debug thing *.options va_mode=debug
* Shows results .print I(p,n) @YVLGVAR[I(p,n)] .print V(r1) V(Vg)
.end
So, can you give me some feedback or what should I read or do, thanks :-[ Seario
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