You'd normally need to put:
Code:INCLUDE $IUSHOME/tools/inca/files/IEEE_vhdlams/cds.lib
in your cds.lib to reference the various VHDL standard libraries.
As for synthesizing VerilogAMS or VHDL-AMS code, I don't believe any tools can do that. There has only been limited success of tools performing Analog Synthesis (it's rather hard to have a general solution; specific tools for specific types of designs have been done, but these (as far as I know) are not normally synthesizing from a VerilogAMS or VHDL-AMS model, but from a specification of some sort).
http://www.edadesignline.com/showArticle.jhtml?articleID=192200530http://www.planetanalog.com/showArticle.jhtml?articleID=12804584Both of the articles are a little old, but I just did a very quick google search. Several of the companies in this area have either been acquired or gone out existence...
Andrew.