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Berti

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Voltage Reliability in Power-Down Mode
Feb 17^th, 2009, 5:37am

Hi everybody,

I have the attached simple vt-reference circuit which uses low voltage (3.3V) transistors but it connected to a high voltage supply (4.2V). In power-down mode, the switches connected to ENA are off. Consequently, the vds of the individual transistors will depend on the leakage path which unfortunately is only poorly control over process and temperature.
Does anybody has an idea how to make sure that the transistors don't see a too high vds (e.g. by adding cascode transistors etc.?)?

Cheers

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NiceFeng New Member Offline Posts: 9	Re: Voltage Reliability in Power-Down Mode Reply #1 - Apr 18^th, 2009, 11:15pm Hi,Berti, My two cents: Do not completely turn off the block, but biasing it with very low current, say 10nA, thus make sure each transistor works in a somewhat predictable status with reasonable Vds. BTW, isn't it a current generator? Can it also be used as a vt-reference circuit? Regards, Feng
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Berti Community Fellow Offline Posts: 356	Re: Voltage Reliability in Power-Down Mode Reply #2 - Apr 20^th, 2009, 11:42pm Hi Feng, Thank for the idea. Quote: BTW, isn't it a current generator? Can it also be used as a vt-reference circuit? It is a current generator. I call it vt-reference as the current is given by I=Vt/R. I think also P. Gray/R. Meyer call this circuit a vt-reference in their book. Cheers
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safwatonline Junior Member Offline Posts: 20	Re: Voltage Reliability in Power-Down Mode Reply #3 - Jul 6^th, 2009, 1:03pm doesn't shorting the gate of the PMOS mirror to Vdd do it?
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