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Dan Clement

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connect modules mystery in Cadence ams designer (OSS flow)
Feb 18^th, 2009, 1:20pm

Forum:

I have a mysterious connect module issue. I have an internal analog signal that connects to an analog pad. The output of the analog pad is getting a connect module for some unknown reason and converting the signal to digital.

The pad side of the path only connects to the stimulus file which defines the port as an electrical inout. The pad schematic is all analog and is used elsewhere in the design without connect module problems. The core side of the signal only connects to one analog output, and does not seem to have connect module troubles.

So the question is how do I debug this type of situation? Using ams designer through ADE, is it possible to not allow connect modules on particular parts of the design?

I am totally at a loss as to how to fix this problem so any ideas on how to debug this would be greatly appreciated. I'm afraid I cannot send the netlist as this is an entire chip that I am simulating.

Thanks and best regards,
Dan

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boe Community Fellow Offline Posts: 615	Re: connect modules mystery in Cadence ams designer (OSS flow) Reply #1 - Feb 19^th, 2009, 8:47am Dan, maybe you have a digital test module that probes the top-level net (through the hierarchy)? BOE
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Dan Clement

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Re: connect modules mystery in Cadence ams designer (OSS flow)
Reply #2 - Feb 19^th, 2009, 9:17am

Hi,

That is an excellent suggestion. Unfortunately I have a mixed signal verilogams testbench that this port is connected to. Inside the testbench the port is defined as electrical and has a cap and resistor connected to this node. It is defined as inout, electrical.

Nothing digital ever touches this net...

That is why I am so stuck...

Thanks for taking the time to respond.

Best Regards,
Dan

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ACWWong

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Re: connect modules mystery in Cadence ams designer (OSS flow)
Reply #3 - Feb 19^th, 2009, 10:29am

Have you tried defining the netDiscipline property in schematic to "electrical" for the offending net ?
If you're not running AMS from a testbench schematic, you can set nets/nodes to be analog or digital by using an OOMR (out-of module reference ?)... an OOMR is simply a line of text in your netlist like:
electrical Instance1.instance2.net1 (this will set net1 in instance2 within instance 1 to be analog).

hope this helps
aw

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Dan Clement

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Re: connect modules mystery in Cadence ams designer (OSS flow)
Reply #4 - Feb 19^th, 2009, 11:57am

I just finished trying out the idea of setting the netDiscipline property on the messed up wire. Unfortunately it did not resolve the problem.

FYI: I have a top level schematic with two instances: one is the chip, and the other is my stimulus block. In the stimulus block (verilogams) the signal is for sure electrical and inout. In the top level schematic there is a wire that connects the stimulus to the chip. Nothing else touches this wire. Inside the chip it goes through an analog pad, where all the views are analog, and goes through a series resistor to the output of the internal cell.

Any other ideas? I am completely stumped by this one...

Thanks,
Dan

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boe Community Fellow Offline Posts: 615	Re: connect modules mystery in Cadence ams designer (OSS flow) Reply #5 - Feb 20^th, 2009, 9:25am Dan, some ideas: Did you check the netlist? Does the top-level cell contain a discipline definition or not? Does the netlist use the views you want? BOE
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Dan Clement

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Re: connect modules mystery in Cadence ams designer (OSS flow)
Reply #6 - Feb 22^nd, 2009, 11:13am

I have done more investigation and found that when using the OSS netlister, even with netDiscipline properties set, that the electrical discipline is stripped off. So since the default discipline is logic and the ports in the netlist are not electrical, the simulator has decided to place a connect module in.

When I do an AMS netlist from the CIW interface, it comes out correctly which means the netDisciplines are forcing the ports to be defined as electrical. I think this netlister is cell view based.

I tried to run cell view based netlisting and that opened up a whole new set of problems that after spending a solid ten hours on I could not figure out how to get cell view based to work. So I put it back to OSS and I'm hoping that someone out there knows of a version of ICFB that solves this problem, or some other type of trick to make this work.

FYI: I did replace the pad schematic with a fully veriloga file that has the discipline defined as electrical. Same problem if you can believe it...

I am really stumped. I think this is going to end up being a bug in the simulator since nothing really seems to be working.

Does anyone else have some ideas? I am in big trouble on schedule if I can't get this resolved.

Thanks,
Dan

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Ken Kundert

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Re: connect modules mystery in Cadence ams designer (OSS flow)
Reply #7 - Feb 22^nd, 2009, 11:26am

Unfortunately, the default discipline algorithm in AMS Designer is a bit too aggressive. You could try simply not specifying a default discipline and then manually putting the logic discipline on all the ports that need it. This tends to work pretty well unless you have a standard cell library that you cannot modify.

Alternatively, you can often work around these kinds of problems by using a hierarchical reference to associated a discipline on a net from the testbench. Put something like this in the testbench ...

electrical DUT.blockN.netM

-Ken

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Dan Clement

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Re: connect modules mystery in Cadence ams designer (OSS flow)
Reply #8 - Feb 22^nd, 2009, 6:27pm

Ken, et al.:

Thanks for the ideas.

I don't think it will be feasible in my design to not use the logic default. However I do see that would probably be a better flow next time.

I tried to force every node as you suggested. I did this from the stimulus verilogams file all the way down to the core cell through the pad frame. It still wants to put this connect module in.

Is OSS something that I should not be using? Is cellview or OSS the best one to use? I'm new to ams so I'm not sure what the experienced designers are using.

How about other ideas? Is it possible there is some stale data of some kind hanging around that overrides the choices I make in the ams file or in the config view? Something behind the scenes?

Thanks,
Dan

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Andrew Beckett

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Re: connect modules mystery in Cadence ams designer (OSS flow)
Reply #9 - Feb 23^rd, 2009, 12:06am

Dan,

I suspect the best thing to do here would be to contact Cadence customer support - it's hard to debug this kind of thing without seeing it, and they could always do a web session with you to take a look.

The two netlisters are there to support different setups. If you have "ams" CDF simInfo for your PDK, then the cell-based netlister will work - if you don't, then you either need to set it up (there's a tool in the Tools->Conversion Toolbox in the CIW for this), or use OSS. The OSS netlister essentially uses the spectre CDF simInfo and translates. I wouldn't say that you shouldn't use OSS, but do make sure you're using a recent ISR of the IC environment as there have been a number of fixes over recent months.

Regards,

Andrew.

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Dan Clement Community Member Offline Posts: 95 Salt Lake City, Utah, USA	Re: connect modules mystery in Cadence ams designer (OSS flow) Reply #10 - Feb 23^rd, 2009, 6:02am Andrew, Thanks. I agree that it's time for support. I will make sure that I am using the most current tools possible with my company CAD team and then if the problem is still there we can take it to cadence support. Thanks for everyone's time. Best Regards, Dan
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Dan Clement

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Salt Lake City, Utah, USA

Re: connect modules mystery in Cadence ams designer (OSS flow)
Reply #11 - Jun 22^nd, 2009, 11:54am

I wanted to close the loop on this issue... It's been a while, but nonetheless something to look out for.

Turns out that I had written some bad code! I had a bunch of similar assignments like this:

I(a,b) <+ I1
...
I(y,z) <+ 12

Note that the 12 is now an integer, not I2 as it should have been!

Good news is that the tools did exactly what they should have by making this a logic discipline. Bad news is it was very hard to find...

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