i'm trying to directly measure in spice where the currents entering the terminals of a transistor flow.  specifically, i want to be able to differentiate between currents charging capacitances and other.

the path i'm heading down is breaking apart one of the verilog-a transistor models, making a standalone verilog module for each of its current sources and then wiring them up in a schematic.  this way i can  descend into the transistor and probe internal branches.

i've been eyeing the models at SIMUCAD, and i also have the "official" EKV2.6 model from the EKV guys.  

good idea, bad idea, general thoughts?

thanks

actually, something like that would work just fine for what i want.

is there a straight forward way to have spice (i mostly use hspice, and spectre, though i am not opposed to other simulators) spit out sorta quasi-steady-state voltages and currents from a time simulation?

to be more specific, what i'd want would be the equivalent functionality of taking take all node voltages as a function of time from a transient simulation.  then use these in a parametric dc sweep to get the currents.

this would be even better, as i wouldn't have to limit myself to only veriloga models.

excellent, this is exactly what i was looking for.

thank you guys so much.