$table_model is part of the Verilog-AMS LRM, so it should be supported. Here's an example, copied from the LRM:
Code:module example_tb(a, b);
electrical a, b;
inout a, b;
analog begin
I(a, b) <+ $table_model(V(a,b),"sample.dat");
end
endmodule
and a completely fabricated data file:
Code:#sample.dat
0 0
1 1
2 4
3 9
4 16