Verilog-AMS models are simulated using AMS Designer, which is included in the "IUS" stream of software (called "LDV" in earlier versions). The simulator is invoked using ncsim (often launched from either ADE, or from the hierarchy editor plugin within Virtuoso, or from the command line).

If you want to use a Cadence mixed-signal simulator that supports Verilog-AMS, you'll need AMS Designer, and so you'll need access to "ncsim".

Regards,

Andrew.