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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › Is it possible to make verilog-A/AMS modules analysis-sensitive?
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Is it possible to make verilog-A/AMS modules analysis-sensitive? (Read 2085 times)
Aigneryu
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Is it possible to make verilog-A/AMS modules analysis-sensitive?
Mar 29th, 2009, 6:22am  
Hi,

I have some frequency meters in my testbench for transient simulation; however, these frequency meters have hidden states,  and I want to skip the part with hidden states in them during the PSS simulation. Is it possible?


Sincerely,
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Geoffrey_Coram
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Re: Is it possible to make verilog-A/AMS modules analysis-sensitive?
Reply #1 - Mar 30th, 2009, 8:51am  
How about this?
Code:
if (analysis("pss", "pac", "pnoise")) begin
  // set freq meter variables to 0 to avoid hidden state
end else begin
  // frequency meter code
end
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