What are t1 and t2 initialized to?  Variables in Verilog-A start at zero, and the cross doesn't trigger during the dc solution, so t1=t2=0 at time=0, and the out_period equation will cause a division by zero.

I'm not sure what the language guarantees regarding the timer event when you change the period.  Suppose you had the timer set to go off at 2us, starting from 0.  Now, at 1us, you change the period to 3us.  Does the timer go off at:
a) 2us, because that event was scheduled and the LRM doesn't specify that it should be deleted?
b) 3us, because the simulator remembers that the timer was set at time 0?
c) 4us, which is 3us after the period was changed?

Actually, c) is wrong, but it reminds me that the first argument is the start time.  So, if you had timer(0,4u) and then at 24.1us, you changed the period to 5u (out_period=10u), then you've just made it timer(0, 5u) and so it will fire at 25us, because that's an integer number of periods from the start time of 0, even though it's only 1us from the last time it fired (24us).

And it looks like the outperiod can Change..
This will make the same mistake as a variable oscillator output implemented as
V(osc) <+ Ampl*cos(2*`M_PI*Freq);

If you Change the variable referenced in the periodic parameter of the timer, your next event will be based on the new period, as applied from the starting time of the timer. .. Not on the new period from the last event.

for a variable (digital) oscillation , you might do better with an always block.
if you are stuck with Verilog-A (rather than AMS) you could just do
Code:

@(timer(next_edge)) begin
  next_edge = $abstime + out_period;
  z = !z;
end
 

good luck, and keep trying

Paul,
   Using last_crossing is an improvement, but you still need the @cross statement. last_crossing is not very accurate without the @cross.

-Ken