I have what might be a very basic question for most of you.

I can not seem to get vdd/gnd delivered to the verilog blocks in my AMS test bench. The verilog code has no mention of supply connections so I thought it must be defined implicitly through the netlister options in the ADE window but that does not help either. Digital components in my test bench appears to be unpowered. Is there some other include file or setup step I am missing here? Here is a basic code example. It might give people here more clues as to what I am doing wrong or missing.

Thanks,
Rehan


// Created by ihdl
`timescale 1ns/1ps

`celldefine

module inv0d0 (ZN, I);
     output ZN;
     input I;
`protect

     specify
           // Pin-to-pin timing.
     (I => ZN) = (`inv0d0_i_hl_zn_lh,`inv0d0_i_lh_zn_hl);
     endspecify

     // Gate-level description.
     not _i0 (ZN,I);

`endprotect
endmodule

`endcelldefine