K,

Here's my suggestion.  In www.DesignersGuide.org, go to the Verilog-AMS Model Library tab and look at the Verilog-AMS model for a comparator. Take that approach in your model.  I think you are using two steps to get your digital output and you only need one.

That is, you can use something like.

always @(above (V(n) - 0.5))  
  begin
      avalid_out = 1'b1;
      avalid = 2;
  end

(Beware, the code above doesn't accomplish your intended function and only serves as an example comparison.)

Also, see the comparator model I refer to above for some timing and voltage resolution options.

If you have further questions you may contact me directly.

Best of luck.

Bob P.

Peruzzi@RPeruzzi.com
www.RPeruzzi.com

K,

I think there are a couple of things going on with your unexpected delay and apparent finite rise time.

This first one is just my guess.  SimVision, if you are using it, might be "connecting the dots" and what is actually a step appears as a ramp.  (One of my friends and colleagues calls this "Lying Mode".) Setting the waveform format of the signal to "Analog Sample and Hold" is a better way to view discrete-time analog signals.

But the major discrepancy you are seeing is because the analog solver works differently than the digital solver.  The analog solver chooses solution time-points using rel-tol, max-tol and max-timestep parameters. The analog solver is in control of this part of your code:

analog
  begin
      if(V(n) < 0.5)
          avalid = 2;
      else
...

On the other hand, your

always @(above...

code creates a more direct link between the analog and digital engines. It forces a nearly simultaneous solution point in both the digital and analog worlds.

This loose linkage between the two solvers can drive you absolutely crazy.  The same circuit, with the same stimulus, can produce different results depending on the simulation stop-time.  Or, again with the same stimulus and the same stop time, adding further but unrelated circuitry with its own stimuli can change the output of the original circuitry.  You must be very conscious of this analog/digital solver relationship as you develop your system and its testbench.  Or you'll get burned and waste weeks debugging!

I may not be putting this exactly right.  It's kind of difficult to distill the concept into a couple of sentences in the time I'm willing to give, so once again I'll give you a reference:

Designers Guide to Verilog-AMS by Kenneth S. Kundert & Olaf Zinke

Use the Designers-Guide.org link to Amazon.com to buy this book. So this community gets a little kick back. You might be able to google up an explanation of how the analog versus digital solver works, but since you are asking this kind of question I think you are in need of reading Ken's book.


If you have further questions you may contact me directly.

Best of luck.

Bob P.

Peruzzi@RPeruzzi.com
www.RPeruzzi.com