jbdavid wrote on May 14th, 2009, 6:34pm:I've not heard satisfactory answers to my questions about using always and analog blocks in the same model.
There is no such limitation.
jbdavid wrote on May 14th, 2009, 6:34pm:-- What I've heard they support is Verilog + Verilog-A
"Nanosim+VCS" supports full Verilog-AMS surely.
However I feel an implemenation of IE(Interface Element) is poor.