Hi!
I want to generate a Verilog-A model for a programmable divider. It has two inputs, clk and control word(division ratio). Is it OK to read the control word and assign the division ratio with it @ initial step, then complete the divider part with the assigned division ratio?

I am pretty new in this area. Thanks a lot.

Hi Lois,

You're correct that you must read the control word @initial_step, but don't forget to respond to any subsequent changes in the control word.

And if the circuit is already designed (that is, you're not designing it from the top-down) make sure the model reacts to control word changes the same way as the circuit.  Try changing the control word at different phases of clk and different states of the numerical counter. (This is a rich area for finding bugs in the design as well as the model.)

Best regards,

Bob P.
www.RPeruzzi.com

Generally the initial block should do initialization.. and an always block should process the control signals and change the value..
After all, you might get more than one value set command.