cmos.analogvala wrote on Jun 13th, 2009, 8:57am:
- This is not the case, as netlist shows that both the device have same model name. The model files are included in Analog Design Environment.
So, what differences are there in the netlist?
a) pin lists are different? could imagine that designkit has a 5- or 6-terminal MOS, to get pmos substrate, or isolated nmos well and substrate
b) instance parameters are different? perhaps the designkit has estimated layout information, such as SA, SB for STI/LOD stress effect.