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cmos.analogvala

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UMC90nm Designkit Transistors vs AnalogLib Transistors in cadence
Jun 11^th, 2009, 11:02pm

What is the different between UMC90nm designkit transistor and analogLib transistor as long as DC characteristics are concerned when simulated with same model files.

I have simulated dc operating point of two transistors, one from analogLib and the other from umc90nm designkit, under the same VGS and VDS and same model files. I see 1uA of difference in the current between the two.

Why so ? I feel these two transistors should be same for dc characteristics.

-Thanks

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Geoffrey_Coram

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Re: UMC90nm Designkit Transistors vs AnalogLib Transistors in cadence
Reply #1 - Jun 12^th, 2009, 10:33am

I don't understand your experiment. Isn't the analogLib transistor just a generic transistor from some older process? How are you using "the same model files" for both? Are you saying you have a schematic where one device uses a symbol from the designkit and the other uses a symbol from analogLib? How then do you get the analogLib device to use the model files? You may be including the model files, but the analogLib device probably doesn't use the .model card from the file.

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cmos.analogvala

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Re: UMC90nm Designkit Transistors vs AnalogLib Transistors in cadence
Reply #2 - Jun 13^th, 2009, 8:57am

Are you saying you have a schematic where one device uses a symbol from the designkit and the other uses a symbol from analogLib?
-Yes
How then do you get the analogLib device to use the model files?
- In analogLib device I gave device model name same as I gave it in UMC90nm designkit
You may be including the model files, but the analogLib device probably doesn't use the .model card from the file.
- This is not the case, as netlist shows that both the device have same model name. The model files are included in Analog Design Environment.

Also, the interesting thing is that with UMC180nm devices the similar experiments (for DC operating point analysis ) concludes that UMC180nm designkit transistors are same as analaog transistor. That is it doesnt matter whether we pick transistor symbol from UMC design kit ot analogLib as long as DC operating point is concerned and same model file is attached.

-CA

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Geoffrey_Coram

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Re: UMC90nm Designkit Transistors vs AnalogLib Transistors in cadence
Reply #3 - Jun 15^th, 2009, 4:38am

cmos.analogvala wrote on Jun 13^th, 2009, 8:57am:

- This is not the case, as netlist shows that both the device have same model name. The model files are included in Analog Design Environment.

So, what differences are there in the netlist?
a) pin lists are different? could imagine that designkit has a 5- or 6-terminal MOS, to get pmos substrate, or isolated nmos well and substrate
b) instance parameters are different? perhaps the designkit has estimated layout information, such as SA, SB for STI/LOD stress effect.

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If at first you do succeed, STOP, raise your standards, and stop wasting your time.

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cmos.analogvala

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Re: UMC90nm Designkit Transistors vs AnalogLib Transistors in cadence
Reply #4 - Jul 1^st, 2009, 12:39pm

Yeah, you were right ..the designkit estimates sa and sb parameters. In the previous experiment we were assigning variables transistor widths. Hence, in the netlist, the designkit transistor didn't have any sa and sb parameters. However in the simulations it was considering some values of sa and sb. When we gave actual value of width of the transistor, in the netlist we could see sa and sb are the extra parameters in designkit transistors ...

thanks a lot ....

CA

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