I am curious if anyone has ever considered tying Verilog / AMS to labview for the purpose of virtual test development using hardware models.  Would be most interested in a true co-simulation that would step through time and pass test commands and measurements between the labview test code and the hardware model written in Verilog-HDL/AMS.  I would think this is possible using PLI but I am not aware of any existing support for this capability.  

I did something similar years (16 years?) ago with SaberVerilog and using GPIB to control some measurement equipment. In my case it wasn't with feedback from the actual measured chips - I was primarily doing it to control the test equipment to get the design into a test state and then measure some of the internal blocks.

So it can be done. I must admit I've forgotten how I did it. It may have been PLI-based (probably not VPI, because it pre-dates VPI), if my memory is correct.

Regards,

Andrew.