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qiushidaren

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Cadence ADE Error
Jul 12^th, 2009, 8:19pm

Hi all,

I�m a novice of analog IC design. I�m designing an LDO these days, but I encountered some troubles using Cadence ADE, I know that besides Ken, there are many friends here who are experts in this field, your suggestions will be highly appreciated.

Here are the troubles I encountered:
1Warning from spectre during hierarchy flattening.
defineQ: Unit of quantity �Q� is changed from �coul� to �C�
defineFreq: Unit of quantity �F� is changed from �N� to �Hz�

2Error found by spectre during hierarchy flattening
Waveform type must be specified if any waveform parameters are given.

3Notice from spectre during IC analysis, during transient analysis �tran�
Gmin=1ps is large enough to noticeably affect the DC solution.
dV(I10.I22.o10)=41.564mV
Use �gmin_check� option to eliminate or expand this report
C0: Initial condition computed between nodes net024 and net038 is in error by 180.586mV.
C2: Initial condition computed for net020 is in error by 178.38mV.
C1: Initial condition computed for net022 is in error by 121.365mV.
To reduce error in computed initial conditions, decrease �rforce�.
However, setting rforce too small may result in convergence difficulties or in the matrix becoming singular.

4Simulating �input.scs� on V490-3
Opening directory input.ahdlcmi/(770)
Compiling ahdlcmi module library.
Failed to compile ahdlcmi module library, see input.ahdlcmi/for details.
Could not open ahdlcmi module library
Input.ahdlcmi/obj/SunOS5.9+gcc/optimize/libahdlcmi.so: openfailed: No such file or directory.
Could not open ahdlcmi module library
Input.ahdlcmi/obj/SunOS5.9+gcc/optimize/libahdlcmi.so: openfailed: No such file or directory.
Could not open ahdlcmi module library
Input.ahdlcmi/obj/SunOS5.9+gcc/optimize/libahdlcmi.so: openfailed: No such file or directory.
Could not open ahdlcmi module library
Input.ahdlcmi/obj/SunOS5.9+gcc/optimize/libahdlcmi.so: openfailed: No such file or directory.

Thank you in advance!

Best regards,
Terry

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Andrew Beckett

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Re: Cadence ADE Error
Reply #1 - Jul 13^th, 2009, 1:39am

1. You must be using an old version of the IC tools. The message comes from the quantity.spectre in the ahdLib - this is auto-included in the spectre netlist in order to support spectreHDL models, which required quantity definitions in the spectre netlist. In years gone by, the quantities in this file conflicted with those defined by default for VerilogA. This was fixed in October 2004, and so anything after IC5141 USR1 should not have this problem.
2. I've normally seen this occur if you have a vsource/isource/port in your schematic, and when you look at the netlist, the type of the source is missing. This usually happens because you didn't do "setenv CDS_Netlisting_Mode Analog" before starting icfb. See sourcelink.cadence.com solution number 1838670
3. Well, if you've not set CDS_Netlisting_Mode to Analog, the chances are that your circuit is completely wrong - so I'd fix that first. May well be that these will go away. What it's telling you is that the auto-inserted gmin resistors are large enough to affect the DC solution. You could try reducing gmin. Also search in this forum, because I think there are a number of posts on this.
4. It failed to compile the VerilogA models. This should not cause you any real problems, but almost certain the best bet could be to use a more recent simulator version (I don't know what you're using). Try the latest MMSIM71 version, and see if that solves it.

Regards,

Andrew.

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qiushidaren Community Member Offline I am a lovely MOSFET! Posts: 86 Chengdu	Re: Cadence ADE Error Reply #2 - Jul 13^th, 2009, 6:10am Hi Andrew, Thank you so much for your detailed explanation, it really helps me a lot. I love designers-guide!
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qiushidaren

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Re: Cadence ADE Error
Reply #3 - Jul 13^th, 2009, 7:30am

BTW, the version our company using is IC5033.

Andrew wrote on Jul 13^th, 2009, 6:10am:

Hi Andrew,

4. It failed to compile the VerilogA models. This should not cause you any real problems, but almost certain the best bet could be to use a more recent simulator version (I don't know what you're using). Try the latest MMSIM71 version, and see if that solves it.

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Andrew Beckett

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Re: Cadence ADE Error
Reply #4 - Jul 13^th, 2009, 8:52am

IC5033 has not been supported for some time (not really surprising, since it was released in 2003).

It would really make sense to use a supported version of both the environment, and the simulator (spectre is now released in a separate stream from the environment, and MMSIM71 is the latest simulator release). If you were to use IC5141, you should ideally use a recent subversion, IC5141 USR6 or later.

Regards,

Andrew.

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qiushidaren

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Re: Cadence ADE Error
Reply #5 - Jul 14^th, 2009, 12:55am

Dear Andrew,

I added a line of "setenv CDS_Netlisting_Mode Analog" in .cshrc, but looks like the problem:

3Notice from spectre during IC analysis, during transient analysis �tran�
Gmin=1ps is large enough to noticeably affect the DC solution.
dV(I10.I22.o10)=41.564mV
Use �gmin_check� option to eliminate or expand this report
C0: Initial condition computed between nodes net024 and net038 is in error by 180.586mV.
C2: Initial condition computed for net020 is in error by 178.38mV.
C1: Initial condition computed for net022 is in error by 121.365mV.
To reduce error in computed initial conditions, decrease �rforce�.
However, setting rforce too small may result in convergence difficulties or in the matrix becoming singular.

is still there, and BTW I simulated it with IC5141 this time.

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vijith

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Re: Cadence ADE Error
Reply #6 - Aug 5^th, 2013, 9:44am

Andrew Beckett wrote on Jul 13^th, 2009, 1:39am:

3. Well, if you've not set CDS_Netlisting_Mode to Analog, the chances are that your circuit is completely wrong - so I'd fix that first. May well be that these will go away. What it's telling you is that the auto-inserted gmin resistors are large enough to affect the DC solution. You could try reducing gmin. Also search in this forum, because I think there are a number of posts on this

I got the same error as described by "qiushidaren" in "3"

Could it be due to the technology library provided by the company which restricts the size of the transistors or is it due the reason explained by yourself in the quoted text. please help me out resolve this problem

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