idriss
Junior Member
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Posts: 14
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Hi JbDavid
Thank yo for your reply, actually what I need is a flag to warn me whether I violated the setup time and I think $setup is doing that,I found out that you could add a notifier in order to get a reg signal ,the only stupid thing about that,it toggles each time there is a violation, it means if before the violation the notifier is level 1 after the violation it will become 0 and vice versa ad when there is no violation the value of the notifier doesn't change. The issue is how to use it within my code because I need to say each time there is a violation put the output op to X ,do you have an idea,I checked for vhdl they have this function called d'stable and it's much more easier they don't toggle anything like within verilog. Maybe there is an other way to check whether I have the correct setup time in verilog,do you have an idea ? Thank you very much
reg notifier
specify // here to check if the setup time is ok $setup(d0, posedge cn,200,notfier); endspecify
always @( cn or cp or d0p or d1p)
begin
op = #tdelay (!violation) ? ((cn && d1p) || (cp && d0p)):1'bx; // if there is a violation of the setup time between cn and d0 put op to x on = ~op;
end
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