I am having some trouble getting the logical and physical library (Synposys Educational 90 nm) to match for two cells (TIEH, TIEL) in Synopsys Design Compiler in topographical mode. The error is as follows:

Error: List of pins mismatched in logic and physical libraries (LIBCHK-213)
Logic library: saed90nm_typ
Physical library: ~/cad/mips32/ref/saed90nm_fr
--------------------------------------------------------------------------------
---
Pin direction Pin type
Cell name Pin name Logic Physical Logic Physical
--------------------------------------------------------------------------------
---
TIEH VDD output Output signal power
TIEL VSS output Output signal ground
--------------------------------------------------------------------------------
---

Basically its complaining that TIEH (tie high)/ TIEL (tie low) have VDD/GND defined as signals in the logical library while they are declared as power/ground in the physical library.

In the logic library, the cells are declared as follows:

cell(TIEH) {
area : 2.7648 ;
dont_touch : true;
dont_use : true;
pin(VDD) {
direction : output;
driver_type : pull_up;
capacitance : 0.0;
function : "1";
}
} /* cell(TIEH) */

cell(TIEL) {
area : 2.7648 ;
dont_touch : true;
dont_use : true;
pin(VSS) {
direction : output;
driver_type : pull_down;
capacitance : 0.0;
function : "0";
}
} /* cell(TIEL) */


Anyone know how I can change this to get the tool to match the pins properly. I've looked at the various documentation. One said to use pg_pin syntax but it doesn't seem to mix/match. The library is written in the old syntax. I tried generating the pg syntax library using add_pg_pin_to_lib but i'm getting errors in that as well.

I don't want to try to regenerate the Milkyway CEL/FRAM view (as is taking a lot of time to figure this out) etc so anybody has any ideas?

Thanks for your time.