Deb,

If all you really want to do is verify connectivity you can vastly simplify and speed up the model by eliminating all functionality, and simply use assertions to monitor and report changes to inputs. Then drive outputs in conjunction with downstream models monitoring their own input connectivity.

However, sometimes they don't really mean it when some folks say they only want to verify connectivity.

You may contact me directly if you'd like further information.

Cheers,

Bob P.
www.RPeruzzi.com

Hi Debjit,

It heavily depends on the size and mostly on the environment in which your model is being used. A buck model that works in a particular environment might have convergence problem when you put it in an integrated circuit. For top level integrated circuit such as a PMU (?) it is better to have very simple models, as suggested already. You may require to have models of different complexity for different situations. For top level connectivity verification I think one should have very simple models. May  be omit stuff like PFM. Just flag a message that the block enters PFM, thats it!!!
This can speed up the whole simulation vastly, and also will have less trouble for the simulators to converge!

Finally, the simulator is also responsible for causing these convergence issues. It may not be entirely that the models are wrong. But then  one of the biggest challanges is to develop a model that works in the given simulator. I assume you are using spectreVerilog (not only spectre) for top level sims. spectreVerilog is even more notorious when it comes to convergence!

Having said all these, it is undoubtedly good to have Verilog-A models that models many behaviors and  yet helps quick simulation at chip level!!!  But then time flies...

hope that helps..
cheers!
Rajdeep