Dipankar
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Dear All,
I am facing the following error in AMS at ncelab phase.
" .... Discipline resolution Pass... Doing auto-insertion of connection elements... NO_GOOD_PKT ), .ACK_processing( ACK_processing ), ....... | ncelab: *E,CUVNAS (./ihnl/XXXXX/ZZZZ/schematic/verilog.vams,540|10): segmentation of a signal between analog ports is illegal.... "
background : trying to run spice level simulation of a digital block with the CDK of std-cell used. Now when I use functional views of the cdk cells the simulation goes fine. But when I use schematic view of the cdk cells in certain modules I face the above issue. Agian for those certain modules if I use functional view things go fine.
Can anyone help ?
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