HdrChopper wrote on Aug 18th, 2009, 6:23pm:You can easily build one with ideal switches, from the analoglib.
These can be controlled by means of a variable you can set....
The cell is simply called "switch".
Hope this helps
Tosei
Hi,
would be a possibility
Actually I target a Verilog-A solution, then I could simply define one variable and I could even sweep it in simulation.
Simply placing shorts or opens to branches...
But I end up with that in many problems in simulation (convergence ...)
Regards,