rajdeep
|
Hi all,
How will spectre simulate case statement in Verilog-A?
case(sum) 0: vnom = 1.2; 1: vnom = 2.3; endcase In the above example will the entire section be simulated at every time point or will it be intelligent enough to simulate the section only when there is a change in sum??
Im curious because what if I have the following statement in conjunction with the above statement..
V(vout,gnd) <+ transition(vnom,td,tr);
If spectre evaluates vnom at every timepoint then the argument of transition will be evaluated at every time point. Wont it slow down the sim unnecessarily?
I have tried to wrap up the case statement within a cross statement just to experiment and frankly speaking there was absolutely no difference!!! But that could be because of the simplicity of the testbench...any thoughts?
Thanks much! Rajdeep
|