Hello Everyone.
Just a quick query.
I have a block of code that needs to run on the leading edge of a clock (so I intend to look at the voltage, if v > a threshold, then run the code).
But I need the code to run for a time longer than the pulse with of the clock, lets say 3 clock cycles. If I use the conditional with a threshold it will see the leading edge but as soon as the simulator runs the block of code again when the clock is low the code I need running will stop, as naturally v is less than the threshold.
Any way I can detect the rising edge and set the code going until a time or event later.
Btw, the code implements a RC time constant discharge. The problem I have at the moment is that as soon as the pulse goes low the discharge stops prematurely.
Thanks.
Ed

You can schedule events in Verilog-A. But Im not sure whether your code is in  Verilog-A or Verilog-AMS. I guess in Verilog-AMS things could be easier for you.

Anyway not sure abt the question!! :-p

Rajdeep