Hi to everybody!
I've just begun learning Verilog-AMS language, and my first concern is the possibility to use the created file in AMS Simulator (in Cadence SPB 16.01).

It's not very clear to me how I can implement a verilogams file in a model; normally I use Design Entry HDL, which theoretically gives the possibility to add parts modeled with Verilog or VHDL.
Nevertheless, I tried to import simple programs (written in a notepad file) using Part Developer, and it gave me plenty of errors.
For example, I tried the first one proposed in the manual:
----------------------------------------------------------
module shiftPlus5(in, out);
input in;
output out;
voltage in, out; //voltage is a signal flow
//discipline compatible with
//electrical, but having a
//potential nature only
analog begin
V(out) <+ 5.0 + V(in);
end
endmodule
----------------------------------------------------------
but I got errors like "Import failed because of an error on line XXX and token 'YYY' in file ZZZ. Correct the input file and reimport."
Any suggestions?

Thank you for the help you'll give me.
Cheers,
Emmanuele

Hi Emmanuele,

I use the AMS Designer in Virtuoso too.
If you are writing verilog-A (the above code I meant) instead of verilog-AMS, then stick at the Spectre simulator as Spectre compiles verilog-A, not verilog-AMS. This would save your licenses.

Cheers,
Riad.