Riad KACED
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Posts: 93
Swindon, UK
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Hi,
Did you look at the profiler ? Does your simulation spend time in the digital or Analog solver ?
When I get slow simulation, I usually look at the inserted connect modules as well. Using either the ncelab -iereport option (available from ADE as a switch) or using the TCL debug from ncsim: > scope -aicm -rec -hier. The ierport gives a good summary at the end.
You case is a bit odd though because your AMS simulation is even slower than your Spice level simulation, isn't it ?
This may be wither:
1. A digital statement hanging around 2. A convergence issue with Verilog-A blocs. 3. A bug somewhere.
What I usually do to narrow down this kind of issues is:
1. I run AMS Designer in Spectre direct like way. In other words, I set up the config so to reproduce the Direct Spectre simulation from within the AMS Designer. I don't use any digital, RTL ... etc. Just transistor level + Verilog-A just as run by spectre outside AMS. Ideally, you simulation would run just as fine as Spectre. If not, it means that the Spectre version used by AMS has got some issues and you need to report this to Cadence Customer Support. Otherwise, if all works fine, then you need to look at the profiler to see where the simulation spends most of the time. You may also need to report you issue to cadence Customer Support.
Cheers, Riad.
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