Hi all,
i'm trying to design a floating point adder using advantage pro and i
simulating it using modelsim
this my code
Code:LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY fp_adder IS
-- Declarations
port(a,b: in std_logic_vector(31 downto 0);
c: out std_logic_vector(31 downto 0)
);
END fp_adder ;
-- hds interface_end
ARCHITECTURE adder OF fp_adder IS
--declaration of sign
signal sa,sb,sc: std_logic:= '0';
--declaration of exponent
signal tea,teb: std_logic_vector(7 downto 0):= (others=>'0');
signal ea,eb,ec: unsigned(7 downto 0):= (others=>'0');
--declaration of mantissa
signal tma,tmb: std_logic_vector(22 downto 0):= (others=>'0');
signal ma,mb,mc: unsigned(22 downto 0):= (others=>'0');
BEGIN
--asignement of sign signals
sa <= a(31);
sb <= b(31);
--assignement of exponent signals
tea <= std_logic_vector(a(30 downto 23));
teb <= std_logic_vector(b(30 downto 23));
ea <= unsigned(tea);
eb <= unsigned(teb);
--assignement of mantissa signals
tma <= std_logic_vector(a(22 downto 0));
tmb <= std_logic_vector(b(22 downto 0));
ma <= unsigned(tma);
mb <= unsigned(tmb);
------------------------------------------------------------------------------------------------------
process(ea,eb,ma,mb,sa,sb)
begin
if(ea > eb)then loop
eb <= eb+1;
mb <= '0'& mb(22 downto 1);
exit when ea=eb;
end loop;
mc <= ma+mb;
ec <= ea;
sc <= sa xor sb;
elsif(eb > ea) then loop
ea <= ea+1;
ma <= '0'& ma(22 downto 1);
exit when ea=eb;
end loop;
mc <= ma+mb;
ec <= ea;
sc <= sa xor sb;
else
mc <= ma+mb;
ec <= ea;
sc <= sa xor sb;
end if;
end process;
c(22 downto 0) <= std_logic_vector(mc);
c(30 downto 23) <= std_logic_vector(ec);
c(31) <= sc;
END adder;
i try to test my desig my put
a =.25 "00000000101000000000000000000000"
b =.25 "00000000101000000000000000000000"
so
sa=0
sb=0
sc=0
tea=000000001
teb=000000001
ea=0000000X --i can't understand why?
eb=0000000X --i can't understand why?
tma=01000000000000000000000
tmb=01000000000000000000000
ma=0X000000000000000000000 --i can't understand why?
mb=0X000000000000000000000 --i can't understand why?
mc=XXXXXXXXXXXXXXXXXXXXXXX but i expect to be ="10000000000000000000000"
plz can you explain why there's unknown bits?