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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › need a Verilog-A sampling and hold model wihout hidden state

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need a Verilog-A sampling and hold model wihout hidden state (Read 2040 times)

fantaci New Member Offline I love analog Posts: 1 tokyo	need a Verilog-A sampling and hold model wihout hidden state Nov 27^th, 2009, 2:44am Hello. it might be a old question. I download the verilog-A sampling and hold model from this website, but it turns out can not be simulated by spectre RF for PSS simulation because it has a hidden state. Can somebody show me any alternative model?
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pancho_hideboo Senior Fellow Offline Posts: 1424 Real Homeless	Re: need a Verilog-A sampling and hold model wihout hidden state Reply #1 - Nov 27^th, 2009, 4:40am See http://www.designers-guide.org/VerilogAMS/
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