Hi,
  I have 2 blocks,one is verilog-A (comparator) module and another is verilog (digital decoder) module. It is actually a conventional flash ADC. I am directly connecting output of verilog-A to verilog module and i modified built-in connect rules.Since my supply voltage is 3.3v, i modified built-in "connectLib.ConnRules_18v_full_fast" which is in ConnectLib library and renamed it as "ConnRules_33v_myrule_fast". I changed "vsupp" to 3.3v , vthi=1.75v , vtlo=1.55,where both vthi and vtlo having equal deviation of 0.1 from (vsupl/2).I am using ic5141 and ius8.2. Design is compiling succesfully but giving error during elaboration.Error are as..

Elaborating the design hierarchy:ncelab: *N,SFEDPL: Deploying new SFE in analog engine.                Discipline resolution Pass...                Doing auto-insertion of connection elements...                Building instance overlay tables: ....ncelab: *F,INTERR: INTERNAL ERROR-----------------------------------------------------------------The tool has encountered an unexpected condition and must exit.Contact Cadence Design Systems customer support about thisproblem and provide enough information to help us reproduce it,including the logfile that contains this error message.  TOOL: ncelab    08.20-s017  HOSTNAME: vlsi6  OPERATING SYSTEM: Linux 2.6.9-67.0.7.ELsmp #1 SMP Wed Feb 27 04:47:23 EST 2008 x86_64  MESSAGE: sv_seghandler - trapno -1-----------------------------------------------------------------ncelab: Memory Usage - 20.8M program + 609.5M data = 630.4M totalncelab: CPU Usage - 0.0s system + 0.1s user = 0.1s total (0.3s, 45.6% cpu)Failed to elaborate ("vin_proj" "twobmode" "config").  

  In netlists,its not showing any modified values, vsupl remained to be 1.8v and also other parameters remained to be that of built in rules only.The procedure i followed for modifying the built-in rules is as it is given in a manuel ,here i attached only the doc of procedure. I also attached simulation log file and netlist file.Thank you..

Hi,
 I changed the values in connect models in ADE itself..But its of the same as that of default values.