ywguo
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Hi Guys,
How do I probe inside a verilog-A module? As well known, signals and variable can be defined in side a verilog-A module. I am simulating a behavioral model written in verilog-A. I want to probe inside the verilog-A module to debug.
The simulation tool is spectre. I use ADE as the GUI interface.
Best Regards, Yawei
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