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The Designer's Guide Community Forum › Simulators › Circuit Simulators › Probe inside a verilog-A module

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Probe inside a verilog-A module (Read 4951 times)

ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Probe inside a verilog-A module Feb 04^th, 2010, 8:46pm Hi Guys, How do I probe inside a verilog-A module? As well known, signals and variable can be defined in side a verilog-A module. I am simulating a behavioral model written in verilog-A. I want to probe inside the verilog-A module to debug. The simulation tool is spectre. I use ADE as the GUI interface. Best Regards, Yawei
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Andrew Beckett Senior Fellow Offline Life, don't talk to me about Life... Posts: 1742 Bracknell, UK	Re: Probe inside a verilog-A module Reply #1 - Feb 5^th, 2010, 2:03am Hi Yawei, In the Outputs->Save All form, set the "saveahdlvars" setting to "all". Then you'll be able to see internal variables in the results browser. Regards, Andrew.
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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: Probe inside a verilog-A module Reply #2 - Feb 6^th, 2010, 8:11pm Thank you, Andrew.
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