Anyone else hear of analog rails eda tools?

I'm curious how well the tools work and if they are used in industry.

www.analograils.com

-Dan

Mein Gott!  Das ist sehr teur!

Wow, that tool better be really good...

Thanks for the reply

...and we support all devices.

Hi Dan

We have just begun the sales process. We have 6 circuit dseigners designing various topologies with the product (switchcap and continuous time circuits) to make sure that we handle all situations. First you build the product, then you sell it. We believe the product is ready to sell starting this month, and we are now meeting with customers. We differ from other EDA companies because we are engineering driven. No marketing people at the company. We believe the best technology will win, and we think we have Cadence beat by a mile. Better schematic <=> layout integration (OA based too). Better routing, better placing, better parasitic extraction, and certainly more integrated and easier to use (push button). The users (circuit designers) like it. People who need the skill language or customize PDK's to secure their jobs don't like us so much.

On the simulation front, Hspice and other simulators are integrated in, and we are actively helping gnucap, which is a free simulator. Our layouts are simulation aware and visa versa. We rely on having all the pieces work together

Cliff

Quote:


Customization is needed because you need to design at least for a specific process. Foundries or tool supplier are in the best position to make this customization but often there is only one tool supported from the foundry and no process supported from the tool vendor. There are exceptions at some of your competitors. But to my understanding of 18 years using the mainstream tool but take a look at all alternatives is the foundry dependence which overlooked.

"The tool works great, really everyone will love it and we will be more productive... but I have to setup all process devices, attributes and checks....and if something goes wrong in my check rules I am liable for the delay and mask ruin"

There are approaches to overcome the tool-process lock situation. But not because the foundries like to open the door for new tool vendors but they are so big that they have to support more than one tool vendor. The key is now to use a more tool independend description to allow a genericPDK. Ironically that is in focus for 65nm and below but a generic process description is much easier for 90nm and above CMOS and BiCMOS. There is a further traction from the designer side to look for a process independ design flow where only late in the design process a mapping to a specific process or process comparison is made. That would also profit from a genericPDK approach.

It will be interessting to see vendor offers which does not point to the tool themselve but to the hole design process.

Hi Cliff,

so PDK generation is a service from Analog Rails. That put again the question of liability on the table.

In 1993 I had to setup a flow for composer, virtuoso and diva. The process foundry supported edge and dracula. So both are from the early cadence. But analysing both tool collections, both from cadence, I end up starting everythink from scratch. There was the famous drac2diva but you have to manually rewrite everything because only 90% was automatic translated, and that in a terriable way.

The problem with a tool-locked PDKs is that some tool-functionality is used which is not supplied by other tools. A very good example is the ivpcell verification. Here a parametric cell is verified not based on geometric layer properties but on the numeric layout generator properties themselve. Some PDK's support both because of calibre,diva and assura. But in this case they limit to what could be checked on both methods.

I did not checked the IPL guide but if the foundry restrict themselve to the physical support there is an open way for any improvement which is based on special tool features and not on specfic foundry support.

For instance modelling and verification of layout compositions based on the principal physical devices avaible should be outside the foundry. How I use multifinger-MOS and model the parasitic inductance, the distributed body substrate, the overrouting parasitic cap to gate finger coupling and so on, is design specific.

Do plan Analog Rails to join IPL? (In addition to the service model)

http://blog.shrinkingviolence.com/2010/02/IPL-design-kit-release.html#more

Here is an example: You can do your entire pileline ADC in less than 1 day.

Set your cap size (sqrt KT/C), set your switch size for settling time, optimize your amplifier.

http://www.analograils.com/videos/demos/optimizer-demonstration

Run the autoplacer (yes, we handle analog switches. Ask your friend who attended our demo), adjust the devices if you like, autoroute (15 minutes), then run your simulations with the REAL layout.

If you want, you can always take the OA database that you created THAT DAY and send out your layout to a low labor place (who will probably steal your IP) and get the "sanctioned inaccurate cells with BS callbacks" to ease your mind for your final layout assembly on our tool or Cadence.