Hi,

There could be a multitude of reasons why this error could have occurred. The best for you to start with is looking at the error explanation from ADE -> Simulation -> Output Log -> Error explanation.

Go through the list of proposals to see whether you could spot what's missing in your case.

It looks like the entity for your VHDL has not been found.
How did you create your VHDL ? Using the VHDL editor from ADE or importing VHDL with vhdlin ?

You may check that your VHDL files are well saved in the Cadence database.  This is an example.

In other words, you have to make sure that both your entity and architecture are both under the same cell (That's the rule of thumb I follow).

Say for example I have an 'or' gate.

1. I create, with VHDL editor, a Cell called 'or_gate', view 'entity'.
Code:

library ieee, std;
use ieee.std_logic_1164.all;

entity or_gate is
    port(
    in1 : in std_logic;
    in2 : in std_logic;
    out1 : out std_logic
    );
end or_gate;
 

If compile is succesful, I would be propmted for the symbol to be created (symbol does not exist yet)

2. I create, with VHDL editor, a Cell called 'or_gate', i.e. same cell as previous but with view 'behavior' this time. View 'behavior' is one architecture of entity 'or_gate'.

Code:

architecture behavior of or_gate is
begin
    process begin
    out1 <= in1 or in2 after 5 Ns;
    wait on in1,in2;
    end process;
end behavior;
 

In the HED, I bind cell 'or_gate' to the desired architecture, i.e. 'behavior' in my case and then launch AMS. All should be fine.

If your architecture and entity are under separate Cadence cells, then I'm doubting AMS would work.

Hope this will give you some clues on how to tackle your issue.

BTW, it is good to mention whether you use the Cell-Based 3-step flow or the OSS 1-step irun flow. I am assuming the former as it is default in ADE.

Regards,
Riad.

Riad,

Thank you for your time.

I had this VHDL from another project, and I just created an entity cell view simply by copying and pasting the code into the VHDL editor.

The problem was that this VHDL had both entity and architecture in the same file, so I followed your example and split the file in two, creating a behavioral cell view and a entity cell view.

I am using the Cell-Based 3-step flow.

After I did this, the simulation completed successfully.

Let me ask you another question, since I have never worked with VHDL before.

Talking with some colleagues, they said that it is usual to have both entity and architecture in the same file.

Is there a way to create a cell view with entity and architecture together and use this cell view?

Thank you again,

Regards,

Hi Raphael,

Sorry, I was not really accurate above.
Yes, you definitely can put everything in the same file, it's not a problem at all.

This is for example a code with entity or_gate and 2 architectures of this entity. In Cadence, I create cell 'rkWorkLib'/'or_gate'/'entity' with the following code.

Code:

library ieee, std;
use ieee.std_logic_1164.all;

entity or_gate is
    port(
    in1 : in std_logic;
    in2 : in std_logic;
    out1 : out std_logic
    );
end or_gate;
-- 1st architecture
architecture behavior1 of or_gate is
begin
    process begin
    out1 <= in1 or in2 after 5 Ns;
    wait on in1,in2;
    end process;
end behavior1;
-- 2nd architecture
architecture behavior2 of or_gate is
begin
    process begin
    out1 <= in1 or in2 after 10 Ns;
    wait on in1,in2;
    end process;
end behavior2;
 

When Cadence compiles this code, it will create view 'entity' alongside with views for architectures behavior1 and behavior2 + symbol if told to do so:

This is what I got in the CIW when compiled the above code:
Quote:


regards,
Riad.