jugemu1234
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Hi,
Can anybody help me debugging following code? When I run this, it ends up DC convergence error around pll_rstb node. These code might look mess. if there is anyway to make this simpler/better, it would be appreciated.
--------------------------------------------- `include "constants.vams" `include "disciplines.vams"
`timescale 1ps/1ps
module rosc ( clk, pll_rstb, test_out, dvdd, dvss, en, enExt, extClk, ib_1u, testEn, trim, turbo, turbo_div8, f160M );
input [7:0] trim; input testEn, enExt, ib_1u, dvdd, dvss, extClk, en, turbo, turbo_div8; output clk, pll_rstb, test_out, f160M;
logic [7:0] trim; logic testEn, enExt, en, turbo, turbo_div8; electrical ib_1u, dvdd, dvss, clk, f160M, test_out, extClk, pll_rstb;
real rin, half_period, freq, adj, jitter, ibias, period, int_clk, int_clk_div8, int_clk_div16, int_clk_div64, int_clk_div512; integer seed, tgl0, tgl1, tgl2, tgl3, tgl4, tgl5;
analog begin
ibias=9*I(dvdd,ib_1u); adj=ibias*4;
if(trim[7]) adj = adj-ibias*2.56; if(trim[6]) adj = adj+ibias*1.28; if(trim[5]) adj = adj+ibias*0.64; if(trim[4]) adj = adj+ibias*0.32; if(trim[3]) adj = adj+ibias*0.16; if(trim[2]) adj = adj+ibias*0.08; if(trim[1]) adj = adj+ibias*0.04; if(trim[0]) adj = adj+ibias*0.02; //frequency freq = 3.5E12*adj+3.4E7; half_period= 0.5/freq; @(timer(half_period, half_period)) tgl0=!tgl0; int_clk = V(dvdd,dvss) * transition(tgl0, 0.0, 100p, 100p);
@(timer(half_period*8, half_period*8)) tgl1=!tgl1; int_clk_div8 = V(dvdd,dvss) * transition(tgl1, 0.0, 100p, 100p);
@(timer(half_period*16, half_period*16)) tgl2=!tgl2; int_clk_div16 = V(dvdd,dvss) * transition(tgl2, 0.0, 100p, 100p);
@(timer(half_period*64, half_period*64)) tgl3=!tgl3; int_clk_div64 = V(dvdd,dvss) * transition(tgl3, 0.0, 100p, 100p);
@(timer(half_period*512, half_period*512)) tgl4=!tgl4; int_clk_div512 = V(dvdd,dvss) * transition(tgl4, 0.0, 100p, 100p); //$display ("freq is %g", freq ) ; //$display ("int_clk is %g", int_clk); //$display ("adj is %g", adj);
if(enExt) begin V(clk)<+ V(extClk); end else begin if(!en) begin V(f160M)<+0; V(clk)<+0; V(test_out)<+0; V(pll_rstb)<+0; end else begin if(turbo) begin V(f160M)<+int_clk; if (turbo_div8) V(clk)<+int_clk_div8; else V(clk)<+int_clk_div16; V(test_out)<+int_clk_div64; V(pll_rstb)<+0; end else begin V(f160M)<+0; V(clk)<+int_clk_div8; V(test_out)<+int_clk_div512; if(int_clk_div512 > 0.75)) begin V(pll_rstb)<+V(dvdd,dvss); end end end end
end
endmodule
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