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Compatibility with Hspice (Read 2634 times)

mohammadfawaz New Member Offline Posts: 4	Compatibility with Hspice Mar 22^nd, 2010, 2:07pm Hello all, I'm new to Verlilog A, and I'm having a problem when trying to compile models that are clock depending such as a counter. How can I use a clock in a model and still be able to use the model in HSPICE? Thank you
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Marq Kole

Senior Member

Offline

Hmmm. That's
weird...

Posts: 122
Eindhoven, The Netherlands

Re: Compatibility with Hspice
Reply #1 - Mar 23^rd, 2010, 2:29am

1. Define an input for the clock signal

Code:

inout clk;
electrical clk;

2. Create an event that checks for the clock's edges:

Code:

@(cross(V(clk) - thresh, +1)) begin
  count = (count > max_count) ? 0 : count + 1;
  outval = (count == 0);
end

3. Contribute a value calculated in the event statement to the output

Code:

V(out) <+ outval;

Hope this helps,
Marq

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mohammadfawaz New Member Offline Posts: 4	Re: Compatibility with Hspice Reply #2 - Mar 23^rd, 2010, 2:56pm Hello, When I try to compile this using HSPICE, I'm getting an error at "@". I have HSPICE A-2008.03. Should I have a new version? Thank you
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mohammadfawaz New Member Offline Posts: 4	Re: Compatibility with Hspice Reply #3 - Mar 23^rd, 2010, 3:09pm Problem solved. I have a problem with includes.. thanx
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