Hi everyone,

 For a few years, I have worked out the offset of simple voltage sense amplifiers (like strong-arm latches) by running monte carlo simulations where one sense amp input is a fixed voltage, and the other sense amp input is a copy of the voltage on a capacitor which gets charged a bit higher if the sense amp senses '0' and charged a bit lower if the sense amp senses '1'. This setup forces the sense amp to reach the metastable state after 10~100 sense/reset cycles, and when it is reached, you can just look at the voltage across the sense amp inputs to see the offset (for that particular MC iteration). After 100 or 1000 MC runs, an accurate idea of the sense amp offset distribution (sigma) emerges. I've even confirmed the accuracy of this procedure measuring a few built wafers.

  Until now, I've been using bulk CMOS processes and the above technique has worked fine. Now I'm starting to work with an SOI process and the above process fails terribly, because of the SOI "history effect". Basically, the sense amp in SOI has some hysteresis, so if a particular sense decision is made, it becomes even easier for the sense amp to make the same decision again, and it will do so unless the input swings a considerable distance in the other direction.

  Now the simulation is a mess. The basic thing that happens is that instead of converging on the sense amplifier's offset, the capacitor constantly charges and discharges, bouncing up and down, because the sense amp output is always a stream like (0000000000111111111100000000000111111111...). I can consider the height of this sawtooth-like wave as a measure of the SOI-induced hysteresis, but what has me scared is the centre of the sawtooth is always far too close to 0 to be realistic (even a tiny basic sense amp appears to have an offset of <1mV, which is just impossible).

 So I'd like to ask: how do people work out the offset of a sense amplifier in SOI? One thing I'm tempted to do is just give up on simulation entirely, take what I know must be the most critical FETs (the pair of input FETs) and just say the entire sense amp offset is equal to the combined offset of those FETs - there are a few offset-versus-size tables in the foundry documentation I can use to work out what those FET offsets are.

 But I don't want to give up simulation without a fight! If anyone has any ideas on how I could run monte carlo simulations of a sense amplifier in an SOI process and make some sense of the results, please tell me!

 P.S. In case anyone is thinking "oh, you have to use body-tied FETs for critical analog things like sense amps to avoid the history effect", bad news: I am using the body-tied FETs!  :(

Thanks - that idea described in that white paper is so darn obvious I'm embarrassed I didn't think of it earlier. I haven't tried it yet but I am certain it will work.    :)