Hii
does someone knows how to use clock in veriloga
i need to do the simulation by giving a frequency of 100hz
am new to this thing,so would be nice if someone tells

you can take my program as this(example)
`include "disciplines.vams"
module equation(y,x);
output y;
input x;
voltage x,y;
analog begin
 V(y)<+V(x)  
end
endmodule

i know theres no need for clock in above,,but just explain how i would write syntax,if i need to make simulation for above program with 100Hz clock,,the code for that..(at falling edge of clock)

thank you