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MLIN simulation question in RFDE (Read 34357 times)
pancho_hideboo
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Re: MLIN simulation question in RFDE
Reply #30 - Apr 29th, 2010, 1:37am
 
liletian wrote on Apr 27th, 2010, 10:52am:
I did not find netlist file in my directory. I attached the totally directory file.
What do you mean by "totally directory file".
Your directory is no more than "cell view" of "test_TL_filter" in your "design library" of "test" not "total directory".

Again do you understand directory structure of data created in Cadence DFII and Cadence ADE ?

liletian wrote on Apr 28th, 2010, 8:59am:
can you please give me the totally directory of the RFDE ADS, so I can have a look?
I can't understand what you mean by "RFDE ADS".

Directory structure of RFDE is basically same as Cadence ADE.
But directory structure of ADS project is different from RFDE.

In ADS, project directory includes both design library and simulation data directory.
On the other hand, in RFDE, project directory means simulation data directory which is different from design library.

In RFDE, total directory means design library, custom reference library, simulation directory(project directory) and analysis state directory.
"cell view" directory is never "total directory" in any meaning.

In ADS, total directory mean one project directory if no other project directory is included.

liletian wrote on Apr 27th, 2010, 10:36am:
Why do you think I do not understand RFDE at all.
I can't understand why you can say you understand RFDE.

Again surely read documentations of Cadence ADE and Agilent ADS and RFDE.
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« Last Edit: Apr 29th, 2010, 8:36am by pancho_hideboo »  
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liletian
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Re: MLIN simulation question in RFDE
Reply #31 - Apr 29th, 2010, 8:38am
 
pancho_hideboo wrote on Apr 29th, 2010, 1:37am:
liletian wrote on Apr 27th, 2010, 10:52am:
I did not find netlist file in my directory. I attached the totally directory file.
What do you mean by "totally directory file".
Your directory is no more than "cell view" of "test_TL_filter" in your "design library" of "test" not "total directory".

Again do you understand directory structure of data created in Cadence DFII and Cadence ADE ?

I did understand some of them after conversation with you. Maybe not all of them.
For example, I know how to generate netlist through Cadence ADE now. but not other ways.


liletian wrote on Apr 28th, 2010, 8:59am:
can you please give me the totally directory of the RFDE ADS, so I can have a look?
I can't understand what you mean by "RFDE ADS".

Directory structures of RFDE is basically same as Cadence ADE.
But directory structure of ADS project is different from RFDE.

In ADS, project directory includes both design library and simulation data directory.
On the other hand, in RFDE, project directory means simulation data directory which is different from design library.

I got this now. Thank you.
In RFDE, total directory means design library, custom reference library, simulation directory(project directory) and analysis state directory.
"cell view" directory is never "total directory" in any meaning.


In ADS, total directory mean one project directory if no other project directory is included.

liletian wrote on Apr 27th, 2010, 10:36am:
Why do you think I do not understand RFDE at all.
I can't understand why you can say you understand RFDE.

Again surely read documentations of Cadence ADE and Agilent ADS and RFDE.


Thank you!
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pancho_hideboo
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Re: MLIN simulation question in RFDE
Reply #32 - May 6th, 2010, 2:42am
 
The following is a netlist for Agilent GoldenGate simulator.
As you can see, this netlist style is very different from Agilent ADSsim and Cadence Spectre.

"SP.gg.expanded.gg" Quote:
network main
{
     variable:
     {
           sweep freq { is_design = 1, max = 10000000000, min = 1000, dec = 21 };
           numeric temp { nom = 25, is_design = 1 };
           numeric tnom { nom = 27, is_design = 1 };
     };
     element:
     {
           lumped c2 C0 (net7,\0) { c = 1e-13 };
           microstrip mlin I4 (net06,net7) { l = 0.005, sub = "MSub1", w = 0.00025, wall1 = 1e+30,
wall2 = 1e+30, dispersion = Kirschning };

           hbsrc spsin PORT1 (net06,\0) { r = 50, type = dc, num = 1 };
           hbsrc spsin PORT2 (net7,\0) { r = 10000000, type = dc, num = 2 };
     };
     data:
     {
           microstrip substrate MSub1 { h = 10.0u, er = 9.6, mur = 1, cond = 1e+50,
hu = 1e+36, t = 0, tand = 0, rgh = 0 };

     };
}

simulation SP
{
     variable:
     {
     };
     analysis:
     {
           s_parameter { scale = 1, temp = 25.0, tnom = 27.0, print_dc_state = 2,
collapse_dc_source = 0, iabstol = 1e-12, sweep_cont = 99, gmin = 1.0e-12, conv_err = 0.100000,
gcomp = 1.000000e-12, pivabs = 1e-50, pivrel = 1e-3, resistor_thresh = 1.000000e-03, big_capacitor = 1e-07,
max_signal_value = 1.000000e+13, print_inventory = 1, print_parameter = 0, print_variable = 1, print_perf = 1,
perf_nb_digit = 4, process_spare = 1, topology_check = 1, multithread = 1, undef_par_behavior = 1,
deprecated_par_behavior = 1, tr_max_iter = 20, integ_method = "gear", integ_order = 2, tran_predict_order = 1,
err_print = 2, use_estimate = 0, print_s_param = 0 };
     };
     probe:
     {
     };
     signal:
     {
           small_signal { nominal_freq = freq };
     };
     specification:
     {
           specification_variable { var = [ freq ] };
     };
     task:
     {
           nominal { };
     };
     info:
     {
           netlister { version = "GoldenGate-4.3.6", buildnumber = 2151, library = "My_RFDE_Test", cell = "test_TL_filter_GG",
view = "schematic" };
           ggparser { version = "4.3.6" };
     };
}
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« Last Edit: May 6th, 2010, 3:50am by pancho_hideboo »  
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