I can't find out any design issue in your post
again.
Your question is no more than easy issue related to specific vendor's simulator.
VNF wrote on May 7th, 2010, 1:18am:Does anybody know how to include transistor mismatch (also cap mismatch) into simulation in Cadence ADE?
There are many simulators working in Cadence ADE.
What simulator do you use ?
I assume you use Cadence Spectre as simulator.
The followings are descriptions for "binning".
VNF wrote on May 7th, 2010, 1:18am:model nch bsim3v3 {
1: type=n minr=1e-60 lmin=1.2e-06 - dxl lmax=2.1e-05 wmin=1.2e-06 dxw wmax=1.01e-04 tnom=25 xl=3e-08
....
....
9: type=n minr=1e-60 lmin=2.4e-07 lmax=5e-07 - dxl wmin=3e-07 wmax=6e-07 - dxw tnom=25 xl=3e-08 + dxl flkmo
....
}
Descriptions for mismatch are like following.
Quote:statistics {
process {
vary toxn dist=gauss std=toxn_std
vary dvthn dist=gauss std=dvthn_std
vary dlxn dist=gauss std=dlxn_std
vary dxwn dist=gauss std=dxwn_std
vary cjn dist=gauss std=cjn_std
vary cjswn dist=gauss std=cjswn_std
vary cjswgn dist=gauss std=cjswgn_std
vary cgon dist=gauss std=cgon_std
vary hdifn dist=gauss std=hdifn_std
}
mismatch {
vary toxn dist=gauss std=mtoxn_std
vary dvthn dist=gauss std=mdvthn_std
vary dlxn dist=gauss std=mdlxn_std
vary dxwn dist=gauss std=mdxwn_std
vary cjn dist=gauss std=mcjn_std
vary cjswn dist=gauss std=mcjswn_std
vary cjswgn dist=gauss std=mcjswgn_std
vary cgon dist=gauss std=mcgon_std
vary hdifn dist=gauss std=mhdifn_std
}
}
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comparator offset simulation (Read 2080 times)