liletian
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Hi Guys I generated a diode through verilogAMS. However, when I simulate the diode, I saw the following error to even generate the netlist. Does anyone have idea what is going on here and how to fix it? I attached the error screen. Thank you
// VerilogA for test, diode, veriloga
`include "constants.vams" `include "disciplines.vams"
module diode (a, c); // saturation current (A) parameter real is=10f from (0:inf); // forward transit time (s) parameter real tf=0 from [0:inf); // zero-bias junction capacitance (F) parameter real cjo=0 from [0:inf); // built-in junction potential (V) parameter real phi=0.7 exclude 0; inout a, c; electrical a, c; branch (a, c) res, cap; real qd; analog begin l(res) <+ is*(limexp(V(res)/$vt) -1); qd = tf*l(res)-2*cjo*phi*sqrt(1-V(cap)/phi); l(cap) <+ ddt(qd); end endmodule
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